Job Description

Job Title: CPU / ASIC / SoC / IP / FPGA Design Verification Engineer

Location: Menlo Park, CA 94025

Job Type: 12+ months of contract

Industry: Semiconductors / Electronics / Embedded Systems

Job Summary:

We are seeking a highly motivated and detail-oriented Design Verification Engineer to join our silicon engineering team. The ideal candidate will be responsible for verifying complex CPU cores, SoCs, ASICs, IP blocks, and/or FPGA-based systems, ensuring functional correctness, performance, and power efficiency.

Key Responsibilities:

• Develop and execute verification test plans for CPU/SoC/FPGA/ASIC/IP designs.
• Build UVM/SystemVerilog-based testbenches and develop reusable verification components.
• Perform block-level and system-level verification including constrained-random testing, assertion-based verification, and coverage analysis.
• Collaborate closely with design, architecture, and firmware teams to understand specifications and define verification strategies.
• Debug RTL and gate-level simulations using tools like VCS, Questa, Verdi, DVE, etc.
• Drive functional coverage closure and ensure high-quality sign-off criteria.
• Support emulation, FPGA prototyping, or post-silicon validation, if required.
• Write scripts and automation tools (Python, Perl, Tcl, shell, etc.) to support the DV flow.
• Participate in design reviews and provide feedback to improve design quality and testability.

Required Skills and Experience:

• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years (for mid-level) / 7+ years (for senior) of experience in RTL design verification.
• Solid experience with SystemVerilog, UVM, Verilog/VHDL, and testbench development.
• Good understanding of CPU microarchitecture, AMBA protocols (AXI, AHB, APB), and SoC integration.
• Strong debugging and problem-solving skills with simulation and waveform tools.
• Familiarity with version control systems (Git/Perforce), issue trackers (JIRA), and CI/CD environments.
• Experience with FPGA prototyping, emulation platforms, or post-silicon debug is a plus.

Preferred Qualifications:

• Experience in low-power verification, clock-domain crossing (CDC), and reset domain crossing (RDC) checks.
• Knowledge of formal verification and tools like JasperGold or Questa Formal.
• Exposure to functional safety (ISO 26262) or security verification.
• Familiarity with RISC-V, ARM, or custom CPU cores.

Tools & Technologies:

• Languages: SystemVerilog, Verilog, VHDL, C/C++, Python, Tcl, Shell
• Frameworks: UVM, VMM, OVM
• Tools: Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, Verdi, SimVision
• Protocols: AMBA (AXI/AHB/APB), PCIe, DDR, Ethernet, USB
• Others: Git, Jenkins, Emulators (Veloce, Palladium), FPGA tools (Vivado, Quartus)

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