Design Verification Engineer Job at EDA CAREERS, (Technology Futures Inc)., Alameda, CA

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  • EDA CAREERS, (Technology Futures Inc).
  • Alameda, CA

Job Description

Job Description

ASIC Design Verification Engineer – FORMAL Bay area #8012

Know how to run formal for design Formal UVM simulation Done formal in chip design company or heavy support

This is not a per se “Design Verification” position but more experienced in FORMAL Design Verification.

My client is a very promising well-funded startup at the cutting edge of integrating LLMs with chip design. - Their team is composed of experts in the fields of AI, software development, and semiconductor design. - Their mission is to accelerate the development of complex silicon by orders of magnitude: cutting cost, time and engineering effort, for the world’s leading chip teams. - Their objective is to find the best and brightest engineers to be part of a small, but growing team of technical engineers ready to work at the intersection of AI, EDA, and systems software. They have already deployed several top innovative customers—from Fortune 100s to cutting-edge AI silicon startups --Their backers are top investors including Khosla Ventures, Cerberus, and Clear Ventures. -Their founders have an amazing background and pedigree, perfect for this venture. This is a great opportunity to grow and become management as they grow.

This totally new approach to chip design is a game changer and with their strong foundation and existing customer base, they are positioned to redefine the landscape of chip design. They help build AI chip design and verification for engineers faster.

Building this platform is just the beginning as they tackle some of the toughest challenges in silicon design. Be the future and help build this transformative approach to how chips are built and be part of a deeply technical team.

Job Description:

They are looking for skilled and passionate Chip Designers or Verification Engineers who have significant experience with VLSI front-end design flows AND FORMAL VERIFICATION to collaborate closely with their ML and software teams. In this unique role, you will apply LLM’s for DV; - You will work on advanced technologies that leverage your design verification experience with ML for innovative chip design solutions; - You will have the opportunity to learn from experienced ML leads and directly contribute to projects for their existing customers; - You will leverage your deep FORMAL skills to impact their totally new and innovative approach to CHIP DESIGN.

This position is ideal for a chip designer who is eager to push beyond traditional roles and explore the frontier of AI-integrated semiconductor design. This terrific opportunity will give you the opportunity to make a real and significant contribution, as they unleash this existing, yet totally new approach to CHIP DESIGN.

Key Responsibilities:

  • Collaborate with ML and software teams to develop advanced, AI-driven chip design solutions.
  • Work with customers to best understand their needs with the team
  • Learn from and work closely with strong ML leads to understand and implement cutting-edge technologies in chip design.
  • Engage directly with customer projects, applying your expertise to develop practical and innovative solutions.
  • Contribute to the integration of LLM technologies into the chip design process, enhancing design efficiency and performance.
  • Stay updated with the latest advancements in chip design and AI/ML technologies to continually improve methodologies and solutions.

Qualifications:

  • 3-10 years hands on experience working on or doing chip verification using FORMAL
  • A thorough understanding of Formal, Simulation, UVM and similar
  • Knowledge in Verification and writing FORMAL and running it for design
  • Working knowledge and experience implementing EDA Formal tools
  • Strong experience in chip design, including a thorough understanding of design verification through tapeout.
  • Solid programming skills (e.g., Python, C/C++, Verilog, SystemVerilog).
  • Experience or interest in AI/ML technologies, especially in the context of LLMs, is highly desirable.
  • Strong problem-solving abilities and a proactive attitude toward learning and innovation.
  • Excellent communication skills and the ability to work effectively in a team-oriented environment.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Software skills with industry Verification tools
  • SW/ML a plus

To learn more about this and other openings, contact Mark Gilbert anytime by email, mark@eda-careers. com or call 305-598-2222x3 . Please include your resume so we can have a more precise conversation.

  • Jasper
  • Verdi
  • VC formal
  • Questa

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